1. Field of the Invention
This disclosure relates to a bottom electrode of a capacitor of a semiconductor device and a method of forming the same, and more particularly to a bottom electrode of a cylindrical shaped capacitor and a method of forming the same.
2. Description of the Related Art
As computers have been widely used in recent years, demands for semiconductor devices have been increased. Accordingly, semiconductor devices with high response speeds and high storage capacities are required. To meet these needs, semiconductor device fabrication techniques have been developed that improve integration density, response speeds, and reliability.
For example, a semiconductor device like a dynamic random access memory (DRAM) device has large storage capacity while information data is freely inputted and/or outputted into and/or from the DRAM device. The DRAM device generally includes a memory cell that stores the information data as the form of charges, and a peripheral circuit area that controls the information data. The memory cell of the DRAM device usually includes one access transistor and one accumulation capacitor.
To achieve highly integrated DRAM devices, various researches have been made on the formation of a capacitor in a minute memory cell thereof so that the DRAM device has sufficient storage capacity. The capacitor may be formed using several methods that ensure sufficient storage capacity. Usually, they involve using a high permittivity material as a dielectric layer or increasing the effective area of the capacitor by employing a hemisphere silicon grain (HSG) growth process.
However, the HSG growth process demands complicated and costly steps, decreasing the productivity of the DRAM devices. Additionally, when a high permittivity material is used as a dielectric layer, the productivity of the DRAM device may also decrease due to process variations when the capacitor is formed.
Accordingly, a method of increasing the height of the capacitor and a method of varying the shape of the capacitor have been developed to obtain sufficient storage capacity of the DRAM device. In these methods, the height and shape of the capacitor are varied while the horizontal size of the capacitor is maintained. For example, a bottom electrode with a fin shape or a cylindrical shape may be provided.
The height of the capacitor is more than about 15,000 Å for a recent Giga-graded DRAM device. Thus, a cylindrical shaped capacitor having a height of more than 15,000 Å is employed to ensure the sufficient storage capacity of the DRAM device.
U.S. Pat. No. 6,228,736 (issued to Lee et. al.) and U.S. Pat. No. 6,080,620 (issued to Jeng) disclose cylindrical shaped capacitors. Generally, when the height of the capacitor increases, the bottom electrode of the capacitor may collapse during the capacitor fabrication process. In particular, the collapse of the bottom electrode frequently occurs when the capacitor has a cylindrical shape because the capacitor exhibits an increasingly unstable structure as the height increases.
Japanese Patent Laid-Open Publication No. 13-57413 discloses a cylindrical shaped capacitor having an improved bottom electrode structure.
FIG. 1 is a schematic cross-sectional diagram illustrating a bottom electrode of a conventional cylindrical shaped capacitor.
Referring to FIG. 1, the bottom electrode 10 of a cylindrical shaped capacitor formed on a substrate 15 has a contact plug 11 formed through an insulation layer pattern 17, and a node 13 connected to the contact plug 11. A pad (not shown) is positioned beneath the contact plug 11.
The node 13 of the bottom electrode 10 is divided into an upper node 13a and a lower node 13b on the basis of their critical dimensions (CD). Here, the critical dimension (CD2) of the lower node 13b is larger than the critical dimension (CD1) of the upper node 13a. When the critical dimension (CD2) of the lower node 13b is larger than the critical dimension (CD1) of the upper node 13a, the cylindrical shaped capacitor structure may be improved.
FIGS. 2A and 2B are cross-sectional diagrams illustrating a conventional method of forming a bottom electrode of a cylindrical shaped capacitor.
Referring to FIG. 2A, after a first insulation layer is formed on a substrate 20, the first insulation layer is patterned to form a first insulation layer pattern 22 having a first contact hole 23.
A conductive material is deposited on the first insulation layer pattern 22 to fill up the first contact hole 23 so that a contact plug 24 for the bottom electrode is formed in the first contact hole 23. Here, the contact plug 24 is electrically connected to a pad (not shown) for the bottom electrode. In other words, the contact plug 24 is formed on the pad.
An etch stop layer 25, a second insulation layer 26 and a third insulation layer 28 are sequentially formed on the first insulation layer pattern 22 and on the contact plug 24. The second insulation layer 26 is formed using a material with an etching rate different from that of the third insulation layer 28.
Referring to FIG. 2B, the third insulation layer 28 is etched to form a third insulation layer pattern 28a having a third contact hole 28b. The portion of the second insulation layer 26 exposed through the third insulation layer pattern 28a is etched to form a second insulation layer pattern 26a having a second contact hole 26b exposing the contact plug 24. The third insulation layer pattern 28a and the second insulation layer pattern 26a are formed by in-situ processes. The etch stop layer 25 is etched when the second insulation layer pattern 26a is formed.
The surface of the contact plug 24 is exposed when the second insulation layer pattern 26a and the third insulation layer pattern 28a are formed. The critical dimension of the second contact hole 26b of the second insulation layer pattern 26a is larger than the critical dimension of the third contact hole 28b of the third insulation layer pattern 28a because the etching rate of the second insulation layer 26 is greater than that of the third insulation layer 28.
Unfortunately, part of the first insulation layer pattern 22 formed on an upper lateral portion (region A) of the contact plug 24 is etched as well. In other words, the upper lateral portion (region A) of the contact plug 24 is etched because the etching rate of the third insulation layer 28 is different from that of the second insulation layer 26. Also, the upper lateral portion (region A) of the contact plug 24 is damaged when the third insulation layer 28 and the second insulation layer 26 are cleaned after the etching process.
During the etching and cleaning processes, the upper lateral portion of the contact plug may be damaged. More specially, an electrical bridge may be generated between adjacent contact plugs when a conductive film for the bottom electrode is formed thereon. If a bridge is generated between the contact plugs, the reliability of a semiconductor device, including the bottom electrode is seriously deteriorated. Embodiments of the invention address these and other disadvantages of the prior art.